Design Engineer V

Design Engineer V

Job Code: SUC-DEE36291
Date: 09-15-2022
Job Description :


• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design.


• Experience running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs.
• Experience in Block-level and Full-chip floor-planning and power grid planning.
• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
• Experience with Python, TCL, Perl programming.


• Bachelor’s degree in Electrical Engineering or equivalent similar experience.
• 10+ years’ experience in physical design.
• Understanding of RTL2GDSII flow and design tapeouts in 10nm/7nm or below process technologies.
• Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
• Experience working with EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus or Calibre.


Job Tags: Python, TCL, Perl programming
Job Location: Menlo Park, CA