Verification Engineer for Memory Controller

Verification Engineer for Memory Controller

Job Code: SUCPA2823
Date: 01-01-1970
Job Description :

Job Title: Verification Engineer for Memory Controller
Job ID: SUCPA2823
Contract: 12 Months +
Location: Remote
Job Category: Engineering
Job Description:
• Significant UVM, System Verilog experience in complex test-benches
• Experience working with DRAM controller, PHYs, memory models is preferred
• Significant experience with general verification flows and metrics
• Excellent debug skills
• Working with big teams across multiple geographies
• 7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
• Strong Verilog/System Verilog knowledge
• Has developed or significantly changed components in UVM testbenches - monitors / checkers / sequences
• Some experience with SVA or formal are preferred.
• Ability to debug design/TB failures using logfiles and waveforms
• Knowledge of scripting language (PYTHON or PERL)
• Strong analytical skills and attention to detail;
• Strong written and communication skills

Job Tags:
Job Location: Remote