Verification Engineer

Verification Engineer

Job Code: SUCSEE2823
Date: 01-01-1970
Job Description :

Verification Engineer for Memory Controller: • Significant UVM, SystemVerilog experience in complex test-benches • Experience working with DRAM controller, PHYs, memory models is preferred • Significant experience with general verification flows and metrics • Excellent debug skills • Working with big teams across multiple geographies EXPERIENCE AND EDUCATION: • 7 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting; • Strong Verilog/SystemVerilog knowledge • Has developed or significantly changed components in UVM testbenches - monitors / checkers / sequences • Some experience with SVA or formal are preferred. • Ability to debug design/TB failures using logfiles and waveforms • Knowledge of scripting language (PYTHON or PERL) • Strong analytical skills and attention to detail. • Strong written and communication skills

Job Tags: DRAM controller, PHYs
Job Location: Santa Clara, California