GPU Block Verification Engineer

Duration: 09 Months

The focus of the role is responsible for all aspects of verification on next generation graphics processors, including testbenches, test libraries, software modeling, Verilog modeling, test development, regressions, and infrastructure development.

THE PERSON:?

• An analytical thinker with problem-solving skills and excellent attention to detail
• Enjoys challenging work in a multi-project team environment using state of the art tools and technology.
• Lifelong learner, always looking to pick up new knowledge, skills, and competencies.
• Must be a self-starter, and able to work independently to complete tasks on schedule.
• Very creative with the ability to produce “out of the box” solutions and high initiative to recognize and solve unassigned but project impacting issues.

?KEY RESPONSIBILITIES:?

• Working with Architects and reads documentation to understand features to be implemented and verified.
• Block level test plan creation with the fully understanding of Design Specification
• UVM block level test bench creation and maintenance
• Block level test creation in directed and random constraints covering all features usage model and corner cases, for both function and performance verification.
• Debugging test failures to determine if it is a design or verification test defect, correcting test issues and working with the design team to correct defects.
• Functional coverage implementation and review to meeting coverage requirements.
• Generating coverage report and reviewing coverage with design team to ensure fully coverage of test scenarios.
• Writing System Verilog Assertions to check the design against specification.
• You might also be responsible for implementing script/tool for Design Verification Automation
• You might also be responsible to use Formal tools to verify the design.

?PREFERRED EXPERIENCE:?

• Must have 6 years of experienced in ASIC verification.
• Must be expert in System Verilog, UVM and proficient in SVA and functional coverage.
• Must have ASIC design knowledge and be able to debug Verilog/System Verilog RTL code using simulation tools.
• Be able to work in Linux and Windows environments.
• Good understanding of digital electronics
• Formal Property Verification (FPV) or Formal SEQ experience is a plus.
• Knowledge of C, C++, TCL, Perl is a plus.
• Good understanding of the Compute Graphics a strong plus
• General tools experience with MS Word, Visio, Excel, and PowerPoint.