RTL Design Engineer

Duration: 12 Months

Candidate will be a member of CT RTL group, responsible for defining, specifying, and implementing future DDR IP.

Responsibilities will include:

• Design/implement various state-of-the-art, DDR PHYs (DDR5)
• Deliver detailed specifications & documentation
• Develop RTL and work closely with multiple cross functional teams, to successfully close the design – example : Work on designs to close timing, lint clean and CDC, work with verification team on planning tests for a feature, adding system verilog assertions to design constraints, participating in code reviews, presenting in waveform reviews.
• The successful candidate will possess:
• Solid knowledge in fundamental digital design techniques, background in DDR5 PHY is a must.
• Verilog coding skills, System Verilog coding and basic C skills are highly desired.
• Experience in analyzing and resolving Clock Domain Crossing, Lint, Synthesis failures, static timing issues.
• Tools such VCS, Spyglass, Verdi, Unix, Perforce, Python, PrimeTime.
• Strong/effective communication skills
• Enthusiastic team-first mentality
• Experience with Unix/Linux environments

Top 3 must have skills:

• DDR5 background
• 8+ years of digital design coding
• Knowledge of all the quality tools like CDC, Lint, reset domain crossing, Voltage domain crossing, UPF writing.

Education:

• BS + ~10 years, MS + ~8 years with relevant experience in electrical engineering and/or computer architecture