RTL Design Engineer

Duration: 12 Months

Payrange: $ 120 - 140 / HR

Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.

KEY RESPONSIBILITIES:?

• Perform RTL design of digital components in Verilog/SystemVerilog.
• Analyze/fix Lint and CDC errors of the components.
• Guarantee quality/timely deliverables meeting project’s schedule.
• Help to improve/automate design process.

PREFERRED EXPERIENCE:?

• Knowledge of RISK-V processor integration Express
• Multi-clock domain designs.
• Design constraints for synthesis and static timing analysis.
• Knowledge of AXI/AMBA protocol
• Knowledge of front-end RTL design tools and methodologies.
• Knowledge of scripting languages?like?Perl, tcl or cshell

EDUCATION:

• Bachelor's or master’s in computer engineering