Senior Logic Design Consultant

Duration: 12 Months

Payrange: $95-115/HR

• Work on IP/Block logic design includes but not limited to: System RAS, Memory ECC, and interface logic designs.
• Communicate with architects and external IP teams. Design MAS work as needed.
• Support on going formal verification on design set up and optimization independently.
• Able to learn/analyze current design database and assists support teams independently.
• Support regression quality checks with DV teams.

REQUIREMENTS:

• Be polite and communicate well with fellow team members.
• Minimum 5 years of logic design experiences. Memory ECC and/or bus parity working experiences will be a plus.
• Efficient with Verilog/System Verilog RTL Design and usual Design skills: lint, timing analysis and improvements.
• Well versed in modern Computer Architecture and memory/cache subsystems.
• Efficient in Unix working environments: set up, general usages, and even some scripting/makefile.