Senior RTL Design Engineer

Duration: 12 Months

Pay Rate: 55 - 90 / Hr. on W2

The Role:

• Microarchitecture development of IP subsystems
• Perform RTL design of digital components.
• Work with functional verification team to meet coverage and quality standards.
• Analyze/fix Lint and CDC errors of the components.
• Guarantee quality/timely deliverables meeting project’s schedule.
• Help to improve/automate design process.
• Support post-silicon product bring-up/debug.

Preferred Experience:?

• 10 years' experience in RTL coding.
• Knowledge of PCIe Gen5 and PIPE specification.
• Knowledge of ASIC development flows.
• Knowledge of system Verilog.
• Multi-clock domain designs.
• Design constraints for synthesis and static timing analysis.
• Knowledge of AXI/AMBA protocol.
• Knowledge of front-end RTL design tools and methodologies.
• Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, DFX, power.
• Verification - coverage, test plan, debug.
• Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal).
• Ability to work and effectively collaborate with partners.
• Experience with RTL simulation tools, RTL linting tools, reset domain crossings, clock domain crossings, synthesis, ram generation (Area, Timing, Power, SEU Tradeoffs),
• knowledge of scripting Languages?Like?Perl, TCL or CSHELL.

Education:

• Bachelor's or master’s in computer engineering.