Silicon DD Engineer IV

SGS_JOB_2843

Engineering
Remote
RTL
SOC Integration
Python
TCL
Verilog
UVM
DFT

Contract - 6 Months

We are seeking a talented and driven Silicon Digital Design Engineer to join our team. In this role, you will be responsible for the architecture, design, integration, and verification of advanced ASIC and SoC solutions. You will collaborate with cross-functional teams to deliver high-performance silicon products from concept to production.

Job Responsibilities:

  • Develop efficient digital microarchitectures and contribute to ASIC digital architecture, design, and verification.
  • Integrate IPs and drive top-level microarchitecture definition and RTL development.
  • Lead chip-level integration, verification plan development, and execution.
  • Supervise the RTL-to-GDS flow, including synthesis and timing closure.
  • Support test program development, chip validation, and product maturity.
  • Collaborate with FPGA engineers for early prototyping and validation.
  • Assist with algorithm analysis, verification, and improvement.
  • Support hand-off and integration of blocks into larger SoC environments.
  • Apply Design for Verification concepts throughout the design process.

Skills:

  • Experience in RTL coding, synthesis, and/or SoC Integration.
  • Strong background in digital design microarchitecture.
  • Familiarity with Verilog/SystemVerilog coding. ;
  • Experience with DFT/Testability requirements and test program definition.
  • Familiarity with high-speed interfaces (PCIe, USB, MIPI).
  • FPGA design experience.

Education/Experience:

  • 4+ years of experience as a Digital Design Engineer and/or Chip Lead.
  • Strong experience in RTL coding, synthesis, and/or SoC integration.
  • Solid background in digital design microarchitecture.
  • Proficiency with Verilog and SystemVerilog coding.
  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • Experience with UPF-based simulation flow.
  • SystemVerilog OVM/UVM experience.
  • Scripting experience with Tcl and Python (or similar). Experience in SoC integration and ASIC architecture.
  • Experience in SoC integration and ASIC architecture.

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